Introduction to Advanced System-on-Chip Test Design and Optimization

• Main Author: Larsson, Erik (Author)
• Corporate Author: SpringerLink (Online service)
• Format: Electronic eBook
• Language: English
• Published: Boston, MA : Springer US, 2005.
• Series: Frontiers in Electronic Testing, 29
• Subjects: Engineering.; Engineering design.; Electrical engineering.; Electronics.; Microelectronics.; Electronic circuits.; Optical materials.; Electronic materials.; Circuits and Systems.; Electrical Engineering.; Electronics and Microelectronics, Instrumentation.; Engineering Design.; Optical and Electronic Materials.

 SOC test design and its optimization is the topic of Introduction to Advanced System-on-Chip Test Design and Optimization. It gives an introduction to testing, describes the problems related to SOC testing, discusses the modeling granularity and the implementation into EDA (electronic design automation) tools. The book is divided into three sections: i) test concepts, ii) SOC design for test, and iii) SOC test applications. The first part covers an introduction into test problems including faults, fault types, design-flow, design-for-test techniques such as scan-testing and Boundary Scan. The second part of the book discusses SOC related problems such as system modeling, test conflicts, power consumption, test access mechanism design, test scheduling and defect-oriented scheduling. Finally, the third part focuses on SOC applications, such as integrated test scheduling and TAM design, defect-oriented scheduling, and integrating test design with the core selection process. 

 Testing Concepts -- Design Flow -- Design for Test -- Boundary Scan -- SOC Design for Testability -- System Modeling -- Test Conflicts -- Test Power Dissipation -- Test Access Mechanism -- Test Scheduling -- SOC Test Applications -- A Reconfigurable Power-Conscious Core Wrapper and its Application to System-on-Chip Test Scheduling -- An Integrated Framework for the Design and Optimization of SOC Test Solutions -- Efficient Test Solutions for Core-Based Designs -- Core Selection in the SOC Test Design-Flow -- Defect-Aware Test Scheduling -- An Integrated Technique for Test Vector Selection and Test Scheduling under ATE Memory Depth Constraint.