Functional Verification of Programmable Embedded Architectures A Top-Down Approach /
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current System-on-Chip design methodology. A critical challenge in validation of such systems is the lack of a golden reference model. As a result, many ex...
| Main Authors: | , |
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| Format: | Electronic eBook |
| Language: | English |
| Published: |
Boston, MA :
Springer US,
2005.
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| Online Access: | Full Text via HEAL-Link |
Internet
Full Text via HEAL-LinkΒΚΠ - Πατρα: ALFd
| Call Number: |
330.01 BAU |
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| Copy 1 | Available |
ΒΚΠ - Πατρα: BSC
| Call Number: |
330.01 BAU |
|---|---|
| Copy 2 | Available |
| Copy 3 | Available |