Functional Verification of Programmable Embedded Architectures A Top-Down Approach /
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current System-on-Chip design methodology. A critical challenge in validation of such systems is the lack of a golden reference model. As a result, many ex...
Κύριοι συγγραφείς: | , |
---|---|
Συγγραφή απο Οργανισμό/Αρχή: | |
Μορφή: | Ηλεκτρονική πηγή Ηλ. βιβλίο |
Γλώσσα: | English |
Έκδοση: |
Boston, MA :
Springer US,
2005.
|
Θέματα: | |
Διαθέσιμο Online: | Full Text via HEAL-Link |
Search Result 1