Leakage in Nanometer CMOS Technologies

• Main Authors: Narendra, Siva G. (Author), Chandrakasan, Anantha (Author)
• Corporate Author: SpringerLink (Online service)
• Format: Electronic eBook
• Language: English
• Published: Boston, MA : Springer US, 2006.
• Series: Series on Integrated Circuits and Systems,
• Subjects: Engineering.; Computer hardware.; Computer-aided engineering.; Electrical engineering.; Electronics.; Microelectronics.; Electronic circuits.; Nanotechnology.; Circuits and Systems.; Computer-Aided Engineering (CAD, CAE) and Design.; Electronics and Microelectronics, Instrumentation.; Computer Hardware.; Electrical Engineering.

Scaling transistors into the nanometer regime has resulted in a dramatic increase in MOS leakage (i.e., off-state) current. Threshold voltages of transistors have scaled to maintain performance at reduced power supply voltages. Leakage current has become a major portion of the total power consumptio...

Table of Contents:

• Taxonomy of Leakage: Sources, Impact, and Solutions
• Leakage Dependence on Input Vector
• Power Gating and Dynamic Voltage Scaling
• Methodologies for Power Gating
• Body Biasing
• Process Variation and Adaptive Design
• Memory Leakage Reduction
• Active Leakage Reduction and Multi-Performance Devices
• Impact of Leakage Power and Variation on Testing
• Case Study: Leakage Reduction in Hitachi/Renesas Microprocessors
• Case Study: Leakage Reduction in the Intel Xscale Microprocessor
• Transistor Design to Reduce Leakage.