Leakage in Nanometer CMOS Technologies
Scaling transistors into the nanometer regime has resulted in a dramatic increase in MOS leakage (i.e., off-state) current. Threshold voltages of transistors have scaled to maintain performance at reduced power supply voltages. Leakage current has become a major portion of the total power consumptio...
Κύριοι συγγραφείς: | , |
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Συγγραφή απο Οργανισμό/Αρχή: | |
Μορφή: | Ηλεκτρονική πηγή Ηλ. βιβλίο |
Γλώσσα: | English |
Έκδοση: |
Boston, MA :
Springer US,
2006.
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Σειρά: | Series on Integrated Circuits and Systems,
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Θέματα: | |
Διαθέσιμο Online: | Full Text via HEAL-Link |
Πίνακας περιεχομένων:
- Taxonomy of Leakage: Sources, Impact, and Solutions
- Leakage Dependence on Input Vector
- Power Gating and Dynamic Voltage Scaling
- Methodologies for Power Gating
- Body Biasing
- Process Variation and Adaptive Design
- Memory Leakage Reduction
- Active Leakage Reduction and Multi-Performance Devices
- Impact of Leakage Power and Variation on Testing
- Case Study: Leakage Reduction in Hitachi/Renesas Microprocessors
- Case Study: Leakage Reduction in the Intel Xscale Microprocessor
- Transistor Design to Reduce Leakage.