Fault-Tolerance Techniques for SRAM-based FPGAs

• Main Authors: Kastensmidt, Fernanda Lima (Author), Carro, Luigi (Author), Reis, Ricardo (Author)
• Corporate Author: SpringerLink (Online service)
• Format: Electronic eBook
• Language: English
• Published: Boston, MA : Springer US, 2006.
• Subjects: Engineering.; Logic design.; Computer software > Reusability.; Engineering design.; Electrical engineering.; Electronics.; Microelectronics.; Optical materials.; Electronic materials.; Electrical Engineering.; Optical and Electronic Materials.; Electronics and Microelectronics, Instrumentation.; Engineering Design.; Performance and Reliability.; Logic Design.

Fault-tolerance in integrated circuits is not an exclusive concern regarding space designers or highly-reliable application engineers. Rather, designers of next generation products must cope with reduced margin noises due to technological advances. The continuous evolution of the fabrication technol...

Table of Contents:

• Radiation Effects in Integrated Circuits
• Single Event Upset (SEU) Mitigation Techniques
• Architectural SEU Mitigation Techniques
• High-Level SEU Mitigation Techniques
• Triple Modular Redundancy (TMR) Robustness
• Designing and Testing a TMR Micro-Controller
• Reducing TMR Overheads: Part I
• Reducing TMR Overheads: Part II
• Final Remarks.