Wafer Level 3-D ICs Process Technology
Wafer Level 3-D ICs Process Technology focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses alternative technology platforms for pre-packaging wafer level 3-D ICs, with an emphasis on wafer-to-wafer stacking. Driven by the need for impro...
Συγγραφή απο Οργανισμό/Αρχή: | |
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Άλλοι συγγραφείς: | , , |
Μορφή: | Ηλεκτρονική πηγή Ηλ. βιβλίο |
Γλώσσα: | English |
Έκδοση: |
Boston, MA :
Springer US,
2008.
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Σειρά: | Integrated Circuits and Systems,
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Θέματα: | |
Διαθέσιμο Online: | Full Text via HEAL-Link |
Πίνακας περιεχομένων:
- Overview of Wafer-Level 3D ICs
- Monolithic 3D Integrated Circuits
- Stacked CMOS Technologies
- Wafer-Bonding Technologies and Strategies for 3D ICs
- Through-Silicon Via Fabrication, Backgrind, and Handle Wafer Technologies
- Cu Wafer Bonding for 3D IC Applications
- Cu/Sn Solid#x2013;Liquid Interdiffusion Bonding
- An SOI-Based 3D Circuit Integration Technology
- 3D Fabrication Options for High-Performance CMOS Technology
- 3D Integration Based upon Dielectric Adhesive Bonding
- Direct Hybrid Bonding
- 3D Memory
- Circuit Architectures for 3D Integration
- Thermal Challenges of 3D ICs
- Status and Outlook.