Wafer Level 3-D ICs Process Technology

• Corporate Author: SpringerLink (Online service)
• Other Authors: Tan, Chuan Seng (Editor), Gutmann, Ronald J. (Editor), Reif, L. Rafael (Editor)
• Format: Electronic eBook
• Language: English
• Published: Boston, MA : Springer US, 2008.
• Series: Integrated Circuits and Systems,
• Subjects: Engineering.; Electronics.; Microelectronics.; Optical materials.; Electronic materials.; Materials > Surfaces.; Thin films.; Electronics and Microelectronics, Instrumentation.; Optical and Electronic Materials.; Surfaces and Interfaces, Thin Films.; Engineering, general.

Wafer Level 3-D ICs Process Technology focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses alternative technology platforms for pre-packaging wafer level 3-D ICs, with an emphasis on wafer-to-wafer stacking. Driven by the need for impro...

Table of Contents:

• Overview of Wafer-Level 3D ICs
• Monolithic 3D Integrated Circuits
• Stacked CMOS Technologies
• Wafer-Bonding Technologies and Strategies for 3D ICs
• Through-Silicon Via Fabrication, Backgrind, and Handle Wafer Technologies
• Cu Wafer Bonding for 3D IC Applications
• Cu/Sn Solid#x2013;Liquid Interdiffusion Bonding
• An SOI-Based 3D Circuit Integration Technology
• 3D Fabrication Options for High-Performance CMOS Technology
• 3D Integration Based upon Dielectric Adhesive Bonding
• Direct Hybrid Bonding
• 3D Memory
• Circuit Architectures for 3D Integration
• Thermal Challenges of 3D ICs
• Status and Outlook.