Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms

We are presently observing a paradigm change in designing complex SoC as it occurs roughly every twelve years due to the exponentially increasing number of transistors on a chip. This design discontinuity, as all previous ones, is characterized by a move to a higher level of abstraction. This is req...

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Bibliographic Details
Main Authors: Kogel, Tim (Author), Leupers, Rainer (Author), Meyr, Heinrich (Author)
Corporate Author: SpringerLink (Online service)
Format: Electronic eBook
Language:English
Published: Dordrecht : Springer Netherlands, 2006.
Subjects:
Online Access:Full Text via HEAL-Link
Table of Contents:
  • Foreword. Preface
  • 1. Introduction
  • 2. Embedded SOC Applications
  • 3. Classification of Platform Elements
  • 4. System Level Design Principles
  • 5. Related Work
  • 6. Methodology Overview
  • 7. Unified Timing Model
  • 8. MP-SOC Simulation Framework
  • 9. Case Study
  • 10. Summary
  • Appendices. A: The OSCI TLM Standard. B: The OCPIP TL3 Channel. C: The Architects View Framework
  • List of Figures. List of Tables. References
  • Index.