Design for Manufacturability and Yield for Nano-Scale CMOS
As we approach the 32 nm CMOS technology node the design and manufacturing communities are dealing with a lithography system that has to print circuit artifacts that are significantly less than half the wavelength of the light source used, with new materials, with tighter pitches, and higher aspect...
Main Authors: | , |
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Corporate Author: | |
Format: | Electronic eBook |
Language: | English |
Published: |
Dordrecht :
Springer Netherlands,
2007.
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Series: | Series on Integrated Circuits and Systems,
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Subjects: | |
Online Access: | Full Text via HEAL-Link |
Table of Contents:
- Random Defects
- Systematic Yield - Lithography
- Systematic Yield - Chemical Mechanical Polishing (CMP)
- Variability & Parametric Yield
- Design for Yield
- Yield Prediction
- Conclusions.