Advanced Verification Techniques: A SystemC Based Approach for Successful Tapeout

"As chip size and complexity continues to grow exponentially, the challenges of functional verification are becoming a critical issue in the electronics industry. It is now commonly heard that logical errors missed during functional verification are the most common cause of chip re-spins, and t...

Πλήρης περιγραφή

Λεπτομέρειες βιβλιογραφικής εγγραφής
Κύριοι συγγραφείς: Singh, Leena (Συγγραφέας), Drucker, Leonard (Συγγραφέας), Khan, Neyaz (Συγγραφέας)
Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
Γλώσσα:English
Έκδοση: Boston, MA : Springer US, 2004.
Θέματα:
Διαθέσιμο Online:Full Text via HEAL-Link
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020 |a 9781402080296  |9 978-1-4020-8029-6 
024 7 |a 10.1007/b105272  |2 doi 
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100 1 |a Singh, Leena.  |e author. 
245 1 0 |a Advanced Verification Techniques: A SystemC Based Approach for Successful Tapeout  |h [electronic resource] /  |c by Leena Singh, Leonard Drucker, Neyaz Khan. 
264 1 |a Boston, MA :  |b Springer US,  |c 2004. 
300 |a XVIII, 376 p.  |b online resource. 
336 |a text  |b txt  |2 rdacontent 
337 |a computer  |b c  |2 rdamedia 
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347 |a text file  |b PDF  |2 rda 
505 0 |a Verification Process -- Using SCV for Verification -- Functional Verification Testplan -- Testbench Concepts using SystemC -- Verification Methodology -- Regression/Setup and Run -- Functional Coverage -- Dynamic Memory Modeling -- Post Synthesis Gate Simulation. 
520 |a "As chip size and complexity continues to grow exponentially, the challenges of functional verification are becoming a critical issue in the electronics industry. It is now commonly heard that logical errors missed during functional verification are the most common cause of chip re-spins, and that the costs associated with functional verification are now outweighing the costs of chip design. To cope with these challenges engineers are increasingly relying on new design and verification methodologies and languages. Transaction-based design and verification, constrained random stimulus generation, functional coverage analysis, and assertion-based verification are all techniques that advanced design and verification teams routinely use today. Engineers are also increasingly turning to design and verification models based on C/C++ and SystemC in order to build more abstract, higher performance hardware and software models and to escape the limitations of RTL HDLs. This new book, Advanced Verification Techniques, provides specific guidance for these advanced verification techniques. The book includes realistic examples and shows how SystemC and SCV can be applied to a variety of advanced design and verification tasks." - Stuart Swan. 
650 0 |a Engineering. 
650 0 |a Computer-aided engineering. 
650 0 |a Electrical engineering. 
650 0 |a Electronic circuits. 
650 1 4 |a Engineering. 
650 2 4 |a Circuits and Systems. 
650 2 4 |a Electrical Engineering. 
650 2 4 |a Computer-Aided Engineering (CAD, CAE) and Design. 
700 1 |a Drucker, Leonard.  |e author. 
700 1 |a Khan, Neyaz.  |e author. 
710 2 |a SpringerLink (Online service) 
773 0 |t Springer eBooks 
776 0 8 |i Printed edition:  |z 9781402076725 
856 4 0 |u http://dx.doi.org/10.1007/b105272  |z Full Text via HEAL-Link 
912 |a ZDB-2-ENG 
912 |a ZDB-2-BAE 
950 |a Engineering (Springer-11647)