Clock Generators for SOC Processors Circuits and Architectures /

• Main Author: Fahim, Amr M. (Author)
• Corporate Author: SpringerLink (Online service)
• Format: Electronic eBook
• Language: English
• Published: Boston, MA : Springer US, 2005.
• Subjects: Engineering.; Electrical engineering.; Electronic circuits.; Circuits and Systems.; Electrical Engineering.

Current literature is filled with textbooks and research papers describing frequency synthesizers from a front-end wireless transceiver perspective. The emphasis has historically been on evaluating the frequency synthesizer’s performance in the frequency domain, i.e. in terms of phase noise and spur...

Table of Contents:

• Phase-Locked Loop Fundamentals
• Low-Voltage Analog Cmos Design
• Jitter Analysis in Phase-Locked Loops
• Low-Jitter PLL Architectures
• Digital PLL Design
• DSP Clock Generator Architectures
• Design for Testability in PLLs
• Clock Partitioning and Skew Control.