Power-Aware Testing and Test Strategies for Low Power Devices
Power-Aware Testing and Test Strategies for Low-Power Devices Edited by: Patrick Girard, Research Director, CNRS / LIRMM, France Nicola Nicolici, Associate Professor, McMaster University, Canada Xiaoqing Wen, Professor, Kyushu Institute of Technology, Japan Managing the power consumption of circuits...
Corporate Author: | |
---|---|
Other Authors: | , , |
Format: | Electronic eBook |
Language: | English |
Published: |
Boston, MA :
Springer US,
2010.
|
Subjects: | |
Online Access: | Full Text via HEAL-Link |
Table of Contents:
- Fundamentals of VLSI Testing
- Power Issues During Test
- Low-Power Test Pattern Generation
- Power-Aware Design-for-Test
- Power-Aware Test Data Compression and BIST
- Power-Aware System-Level Test Planning
- Low-Power Design Techniques and Test Implications
- Test Strategies for Multivoltage Designs
- Test Strategies for Gated Clock Designs
- Test of Power Management Structures
- EDA Solution for Power-Aware Design-for-Test.