Low Power Networks-on-Chip
Low Power Networks-on-Chip Edited by: (editors) Cristina Silvano Marcello Lajolo Gianluca Palermo In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and res...
Συγγραφή απο Οργανισμό/Αρχή: | SpringerLink (Online service) |
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Άλλοι συγγραφείς: | Silvano, Cristina (Επιμελητής έκδοσης), Lajolo, Marcello (Επιμελητής έκδοσης), Palermo, Gianluca (Επιμελητής έκδοσης) |
Μορφή: | Ηλεκτρονική πηγή Ηλ. βιβλίο |
Γλώσσα: | English |
Έκδοση: |
Boston, MA :
Springer US : Imprint: Springer,
2011.
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Θέματα: | |
Διαθέσιμο Online: | Full Text via HEAL-Link |
Παρόμοια τεκμήρια
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Error Control for Network-on-Chip Links
ανά: Fu, Bo, κ.ά.
Έκδοση: (2012) -
Reliability, Availability and Serviceability of Networks-on-Chip
ανά: Cota, Érika, κ.ά.
Έκδοση: (2012) -
Power-Aware Testing and Test Strategies for Low Power Devices
Έκδοση: (2010) -
Low Power Design with High-Level Power Estimation and Power-Aware Synthesis
ανά: Ahuja, Sumit, κ.ά.
Έκδοση: (2012) -
Low-Power Variation-Tolerant Design in Nanometer Silicon
Έκδοση: (2011)