Low Power Networks-on-Chip
Low Power Networks-on-Chip Edited by: (editors) Cristina Silvano Marcello Lajolo Gianluca Palermo In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and res...
Συγγραφή απο Οργανισμό/Αρχή: | |
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Άλλοι συγγραφείς: | , , |
Μορφή: | Ηλεκτρονική πηγή Ηλ. βιβλίο |
Γλώσσα: | English |
Έκδοση: |
Boston, MA :
Springer US : Imprint: Springer,
2011.
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Θέματα: | |
Διαθέσιμο Online: | Full Text via HEAL-Link |
Πίνακας περιεχομένων:
- Network-on-Chip Power Estimation
- Timing
- synchronous/asynchronous communication
- Network-on-Chip link design
- Topology exploration
- Network-on-Chip support for CMP/MPSoCs
- Network design for 3D stacked logic and memory
- Beyond the wired Network-on-Chip.