Long-Term Reliability of Nanometer VLSI Systems Modeling, Analysis and Optimization /

• Κύριοι συγγραφείς: Tan, Sheldon (Συγγραφέας, http://id.loc.gov/vocabulary/relators/aut), Tahoori, Mehdi (http://id.loc.gov/vocabulary/relators/aut), Kim, Taeyoung (http://id.loc.gov/vocabulary/relators/aut), Wang, Shengcheng (http://id.loc.gov/vocabulary/relators/aut), Sun, Zeyu (http://id.loc.gov/vocabulary/relators/aut), Kiamehr, Saman (http://id.loc.gov/vocabulary/relators/aut)
• Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
• Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
• Γλώσσα: English
• Έκδοση: Cham : Springer International Publishing : Imprint: Springer, 2019.
• Έκδοση: 1st ed. 2019.
• Θέματα: Electronic circuits.; Microprocessors.; Electronic Circuits and Devices.; Circuits and Systems.; Processor Architectures.

This book provides readers with a detailed reference regarding two of the most important long-term reliability and aging effects on nanometer integrated systems, electromigrations (EM) for interconnect and biased temperature instability (BTI) for CMOS devices. The authors discuss in detail recent de...

Πίνακας περιεχομένων:

• Part I. New physics-based EM analysis and system-level dynamic reliability management
• Chapter 1. Introduction
• Chapter 2. Physics Based EM Modeling
• Chapter 3. Fast EM Stress Evolution Analysis Using Krylov Subspace Method
• Chapter 4. Fast EM Immortatlity Analysis For Multisegment Copper Interconnect Wires
• Chapter 5. Dynamic EM Models For Transient Stress Evolution and Recovery
• Chapter 6. Compact EM Models for Multi-SEgment Interconnect Wires
• Chapter 7. EM Assesment for Power Grid Networks
• Chapter 8. Resource Based EM Modeling for Multi-Crore Microprocessors
• Chapter 9. DRM and Optimization for Real Time Embedded Systems
• Chapter 10. Learning Based DRM and Energy Optimization for Many Core Dark Silicaon Processors
• Chapter 11. Recovery Aware DRM for Near Threshold Dark Silicon Processors
• Chapter 12. Cross-Layer DRM and Optimization For Datacenter Systems
• Part II. Transistor Aging Effects and Reliability
• 13. Introduction
• Chapter 14. Aging AWare Timings Analysis
• Chapter 15. Aging Aware Standard Cell Library Optimization Methods
• Chapter 16. Aging Effects In Sequential Elements
• Chapter 17. Aging Guardband Reduction Through Selective Flip Flop Optimization
• Chapter 18. Workload Aware Static Aging Monitoring and Mitigation of Timing Critical Flip Flops
• Chapter 19. Aging Relaxation at Micro Architecture Level Using Special NOPS
• Chapter 20. Extratime Modelling and Analyis of Transistor Agin at Microarchitecture Level
• Chapter 21. Reducing Processor Wearout By Exploiting The Timing Slack of Instructions.