A Pipelined Multi-core MIPS Machine Hardware Implementation and Correctness Proof /
This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory. The...
| Main Authors: | , , |
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| Corporate Author: | |
| Format: | Electronic eBook |
| Language: | English |
| Published: |
Cham :
Springer International Publishing : Imprint: Springer,
2014.
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| Series: | Lecture Notes in Computer Science,
9000 |
| Subjects: | |
| Online Access: | Full Text via HEAL-Link |
Internet
Full Text via HEAL-LinkΒΚΠ - Πατρα: ALFd
| Call Number: |
330.01 BAU |
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| Copy 1 | Available |
ΒΚΠ - Πατρα: BSC
| Call Number: |
330.01 BAU |
|---|---|
| Copy 2 | Available |
| Copy 3 | Available |