Advanced HDL Synthesis and SOC Prototyping RTL Design Using Verilog /

• Κύριος συγγραφέας: Taraate, Vaibbhav (Συγγραφέας, http://id.loc.gov/vocabulary/relators/aut)
• Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
• Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
• Γλώσσα: English
• Έκδοση: Singapore : Springer Singapore : Imprint: Springer, 2019.
• Έκδοση: 1st ed. 2019.
• Θέματα: Electronic circuits.; Microprogramming .; Logic design.; Circuits and Systems.; Control Structures and Microprogramming.; Logic Design.

This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrat...