Παραπομπή σε μορφή APA (7η εκδ.)

Taraate, V., & Taraate, V. (2019). Advanced HDL Synthesis and SOC Prototyping: RTL Design Using Verilog (1st ed. 2019.). Springer Singapore : Imprint: Springer. https://doi.org/10.1007/978-981-10-8776-9

Παραπομπή σε μορφή Chicago (17η εκδ.)

Taraate, Vaibbhav, και Vaibbhav Taraate. Advanced HDL Synthesis and SOC Prototyping: RTL Design Using Verilog. 1st ed. 2019. Singapore: Springer Singapore : Imprint: Springer, 2019. https://doi.org/10.1007/978-981-10-8776-9.

Παραπομπή σε μορφή MLA (8th εκδ.)

Taraate, Vaibbhav, και Vaibbhav Taraate. Advanced HDL Synthesis and SOC Prototyping: RTL Design Using Verilog. 1st ed. 2019. Springer Singapore : Imprint: Springer, 2019. https://doi.org/10.1007/978-981-10-8776-9.