Advanced HDL Synthesis and SOC Prototyping RTL Design Using Verilog /

This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrat...

Πλήρης περιγραφή

Λεπτομέρειες βιβλιογραφικής εγγραφής
Κύριος συγγραφέας: Taraate, Vaibbhav (Συγγραφέας, http://id.loc.gov/vocabulary/relators/aut)
Συγγραφή απο Οργανισμό/Αρχή: SpringerLink (Online service)
Μορφή: Ηλεκτρονική πηγή Ηλ. βιβλίο
Γλώσσα:English
Έκδοση: Singapore : Springer Singapore : Imprint: Springer, 2019.
Έκδοση:1st ed. 2019.
Θέματα:
Διαθέσιμο Online:Full Text via HEAL-Link
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100 1 |a Taraate, Vaibbhav.  |e author.  |4 aut  |4 http://id.loc.gov/vocabulary/relators/aut 
245 1 0 |a Advanced HDL Synthesis and SOC Prototyping   |h [electronic resource] :  |b RTL Design Using Verilog /  |c by Vaibbhav Taraate. 
250 |a 1st ed. 2019. 
264 1 |a Singapore :  |b Springer Singapore :  |b Imprint: Springer,  |c 2019. 
300 |a XXI, 307 p. 263 illus., 196 illus. in color.  |b online resource. 
336 |a text  |b txt  |2 rdacontent 
337 |a computer  |b c  |2 rdamedia 
338 |a online resource  |b cr  |2 rdacarrier 
347 |a text file  |b PDF  |2 rda 
505 0 |a Introduction -- SOC Design -- RTL Design Guidelines -- RTL Design and Verification -- Processor cores and Architecture design -- Buses and protocols in SOC designs -- DSP Algorithms and Video Processing -- ASIC and FPGA Synthesis -- Static Timing Analysis -- SOC Prototyping -- SOC Prototyping guidelines -- Design Integration and SOC synthesis -- Interconnect delays and Timing -- SOC Prototyping and debug techniques -- Testing at the board level. 
520 |a This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrated Circuit (ASIC) designs. Prototyping using modern high density Field Programmable Gate Arrays (FPGAs) is discussed in this book with the practical examples and case studies. The book discusses SOC design, performance improvement techniques, testing and system level verification, while also describing the modern Intel FPGA/XILINX FPGA architectures and their use in SOC prototyping. Further, the book covers the Synopsys Design Compiler (DC) and Prime Time (PT) commands, and how they can be used to optimize complex ASIC/SOC designs. The contents of this book will be useful to students and professionals alike. 
650 0 |a Electronic circuits. 
650 0 |a Microprogramming . 
650 0 |a Logic design. 
650 1 4 |a Circuits and Systems.  |0 http://scigraph.springernature.com/things/product-market-codes/T24068 
650 2 4 |a Control Structures and Microprogramming.  |0 http://scigraph.springernature.com/things/product-market-codes/I12018 
650 2 4 |a Logic Design.  |0 http://scigraph.springernature.com/things/product-market-codes/I12050 
710 2 |a SpringerLink (Online service) 
773 0 |t Springer eBooks 
776 0 8 |i Printed edition:  |z 9789811087752 
776 0 8 |i Printed edition:  |z 9789811087776 
856 4 0 |u https://doi.org/10.1007/978-981-10-8776-9  |z Full Text via HEAL-Link 
912 |a ZDB-2-ENG 
950 |a Engineering (Springer-11647)