Advanced HDL Synthesis and SOC Prototyping RTL Design Using Verilog /

• Main Author: Taraate, Vaibbhav (Author, http://id.loc.gov/vocabulary/relators/aut)
• Corporate Author: SpringerLink (Online service)
• Format: Electronic eBook
• Language: English
• Published: Singapore : Springer Singapore : Imprint: Springer, 2019.
• Edition: 1st ed. 2019.
• Subjects: Electronic circuits.; Microprogramming .; Logic design.; Circuits and Systems.; Control Structures and Microprogramming.; Logic Design.

This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrat...