| Περίληψη: | In this work, at first we analyze and evaluate, the already known test data compression schemes for post-manufacturing testing and the DFT mechanisms for the enhancement of in-field testing and circuit reliability. We propose a new dictionary based test data compression method for post-manufacturing testing and we discuss several aspect of the testing procedures, as the reusability of the on-chip decoder for the testing of multiple cores, the reusability of the tester vector memory (local memory of the test head), the on-chip implementation cost of the decoder and the test power consumption. Moreover, we improve each of the aforementioned parameters without degradation of the compression and test application time reduction, efficiency of the proposed dictionary coding scheme. We extend our discussion to the in-field testing, revealing that the already known techniques are characterized from their vast intrusiveness to the normal operation of the circuit, resulting to severe performance degradation and, therefore, they are rarely applied (on startup/shutdown of the system and/or on maintenance time windows). To this end, we proposed two new schemes, in the first scheme, we developed a preemptive Built-In Self-Test (BIST) mechanism that ensures none or minimum intrusiveness to the normal operation of the circuit and in the second scheme, we designed a new storage cell for the hardening of the circuit against radiation-induced soft-errors that outperforms the already known designs. Combining the above two schemes, the frequency of in-field testing can be increased for the detection of permanent delay and/or stuck-at faults due to aging, but also the normal operation of the circuit is protected against soft-errors. Therefore, the reliability of the circuit operation is significantly improved.
|
|---|
