| Summary: | This thesis deals with the design and implementation of an FPGA based time to digital
converter by employing a tapped delay line. Several issues regarding the implementation
that are dealt with include clock skew, jitter and non linearity. A down-sampling ap-
proach is proposed in order to improve the performance of the TDC, while the converter
is characterised by a timing experiment that uses clock signals provided by the FPGA
clock manager. While the trade-o s regarding the various operation modes are being
presented, this thesis also discusses the theory of time to digital converters as well as
various circuit implementations. Finally, we also discuss the advantages of TDCs, when
taking into account technology scaling, as well as the processing of signals in the time
domain.
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