Design of fractional-order controller for motion control systems

Recent developments in the field of analog integrated circuits have led to a new interest in circuitry design process, utilizing fractional calculus. Fractional-order models of real systems are undoubtedly more adequate than usually used integer order models, especially concerning control theory and...

Πλήρης περιγραφή

Λεπτομέρειες βιβλιογραφικής εγγραφής
Κύριος συγγραφέας: Μαλατέστα, Ραφαηλία
Άλλοι συγγραφείς: Malatesta, Rafailia
Γλώσσα:English
Έκδοση: 2021
Θέματα:
Διαθέσιμο Online:http://hdl.handle.net/10889/14608
Περιγραφή
Περίληψη:Recent developments in the field of analog integrated circuits have led to a new interest in circuitry design process, utilizing fractional calculus. Fractional-order models of real systems are undoubtedly more adequate than usually used integer order models, especially concerning control theory and motion control systems. Related applications have not yet been fully realized, primarily due to the commercially unavailable way of using fractional-order capacitors in the standard topologies. Previous studies have suggested as an alternative approach to implement fractional-order controllers, the realization of rational transfer functions that approximate their respective fractional-order transfer functions. While significant research has been carried out on fractional-order PID (FOPID) controllers, only few studies have attempted to investigate fractional-order [PD] (FO[PD]) controller. A review of the research that has been conducted on the design of fractional-order controller for motion control systems is initially performed in this M.Sc. Thesis. The main purpose of the study is the approximation of the controller transfer function, using Padé approximation method and consequently the circuitry implementation. The FO[PD] controller realization takes place, utilizing Operational Transconductance Amplifiers (OTAs), in order to achieve electronic tuning of the controllers’ characteristics. The required CMOS OTAs topology is performed using MOS transistors biased in the subthreshold region, which allows operation with low-voltage and low-power dissipation. The performance of the presented structures is evaluated through the derived simulation results, using Cadence software and the Design Kit provided by the Austria Mikro Systeme (AMS) CMOS 0.35μm technology