| Περίληψη: | This work experimented with using a custom instruction set extension for performing the multiply and accumulate instruction which is critical for the Transient State Estimation algorithm. Custom modules were designed and implemented on a RISC-V processor core. The open- source nature of RISC-V makes it an ideal base to implement the extra hardware required to handle those specific workloads. The aim being to both speed up the computation and to reduce transmission data. The central strategy is to use a small core with specialized acceleration instead of a bigger core with excess features, in order to meet the project’s potential future of fitting a processor on the same die as other electronics. An attempt was also made to load the final design on the RISC-V core on PULPissimo . Emphasis is placed on System Verilog modules of multiply and accumulate, behavioral simulation of the designs and then on the interconnections of the designed modules and the core modules.
It was found that the precision of the results are marginally within acceptable limits. Precision measurements were done against random data generated from C code. By measuring the cycle count of computations, it was possible to compare the speed of different implementations. In this case it was found that with the new modifications the time to compute the desired vector is in fact reduced in most implementations .It was found that with the timing paths introduced by the new modules the maximum frequency is reduced .
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