Polar decoder algorithms and hardware architectures for 5G new radio modems

Polar codes have been included in channel coding, along with LDPC codes, for 5G New Radio communication systems, in order to achieve lower power consumption and high performance results. Polar coding is used for control information because of the exceptional correction ability when small codewords a...

Πλήρης περιγραφή

Λεπτομέρειες βιβλιογραφικής εγγραφής
Κύριος συγγραφέας: Λιακοπούλου, Αριστέα
Άλλοι συγγραφείς: Liakopoulou, Aristea
Γλώσσα:English
Έκδοση: 2022
Θέματα:
Διαθέσιμο Online:https://hdl.handle.net/10889/23728
Περιγραφή
Περίληψη:Polar codes have been included in channel coding, along with LDPC codes, for 5G New Radio communication systems, in order to achieve lower power consumption and high performance results. Polar coding is used for control information because of the exceptional correction ability when small codewords are applied. In order to do so, external modes need to be applied in the encoding- decoding chain. Three interleaves are used. CRC interleaver cuts short decoding paths when an uncorrectable error has been detected, Sub-block interleaver and channel interleaver are used in order to improve the error correction performance of the decoder. Three rate matching procedures are used in order to achieve the required data rate, those are puncturing, shortening and repetition. More mechanisms are decided by the standard to be included in decoding chain and they would be studied in extent in this thesis. Due to variations in uplink and downlink control information’s re- quirements and external modes, predefined by 3GPP, different algorithms and architectures will be considered. Successive Cancellation (SC), Successive Cancellation List (SCL), CRC Aided Successive Cancellation List (CA-SCL), Distributed CRC Aided Successive Cancellation List (DCA-SCL) are the al- gorithms mentioned in the standard of 3GPP, but not strictly so we may consider some other algorithms such as Successive Cancellation Flip (SCF) in order to achieve low complexity and high performance. The trade-offs be- tween complexity and error correction will be studied in any case described by the standard and after the evaluation of various decoding algorithms, there will be the hardware implementations adjusting to the requirements of the standard.