High level synthesis architectures of neural network to accelerate handwritten digit recognition

Neural networks have achieved impressive results in a wide range of applications. However, designing and optimizing neural networksfor hardware implementation can be a challenging task due to the complex computations involved. High level synthesis (HLS) is a promising approach that allows hardwar...

Πλήρης περιγραφή

Λεπτομέρειες βιβλιογραφικής εγγραφής
Κύριος συγγραφέας: Παπαδόπουλος, Παναγιώτης Βασίλειος
Άλλοι συγγραφείς: Papadopoylos, Panagiotis Vasileios
Γλώσσα:English
Έκδοση: 2023
Θέματα:
Διαθέσιμο Online:https://hdl.handle.net/10889/25299