High level synthesis architectures of neural network to accelerate handwritten digit recognition

Neural networks have achieved impressive results in a wide range of applications. However, designing and optimizing neural networksfor hardware implementation can be a challenging task due to the complex computations involved. High level synthesis (HLS) is a promising approach that allows hardwar...

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Bibliographic Details
Main Author: Παπαδόπουλος, Παναγιώτης Βασίλειος
Other Authors: Papadopoylos, Panagiotis Vasileios
Language:English
Published: 2023
Subjects:
Online Access:https://hdl.handle.net/10889/25299