High level synthesis architectures of neural network to accelerate handwritten digit recognition

• Κύριος συγγραφέας: Παπαδόπουλος, Παναγιώτης Βασίλειος
• Άλλοι συγγραφείς: Papadopoylos, Panagiotis Vasileios
• Γλώσσα: English
• Έκδοση: 2023
• Θέματα: High level synthesis; Handwritten digit recognition acceleration; Συνθεση υψηλού επιπέδου; Επιτάχυνση αναγνώρισης χειρόγραφων ψηφίων

Neural networks have achieved impressive results in a wide range of applications. However, designing and optimizing neural networksfor hardware implementation can be a challenging task due to the complex computations involved. High level synthesis (HLS) is a promising approach that allows hardware designers to write high-level descriptions of hardware circuits and automatically generate optimized low-level hardware implementations. In this diploma thesis, we investigate the use of HLS, with Vivado HLS framework, to optimize a fully connected neural network for digit recognition. HLS is a design process that takes as input an algorithmic description of a certain function, and outputs a digital hardware implementation of the function. Specifically, we explore the use of HLS tools to automatically generate hardware circuits that implement the neural network, and to optimize the circuit for performance and area. We also investigate the impact of various design choices, such as the number of layers and neurons and techniques who affect the RTL implementation, on the performance of the optimized circuit. There are four different architectures proposed including the Baseline. Furthermore, through an exploration of different parameters of the model we arrive at some interesting conclusions. To evaluate the effectiveness of our approach, we compare the performance and the FPGA’s utilization resources of the optimized circuit with that of a software-based implementation of the neural network. Our results show that the HLS-generated hardware circuit achieves significantly higher performance and lower power consumption compared to the software-based implementation. All implementations use the part xcvu35p-fsvh2892-1-e which belongs to the Virtex UltraScale+ family and the period of the clock is set at 10 nanoseconds. Overall, this diploma thesis demonstrates the potential of HLS for optimizing neural networks for hardware implementation and provides insights into the design and optimization of hardware circuits for machine learning applications.