VHDL for logic synthesis /

• Main Author: Rushton, Andrew, 1962-
• Format: eBook
• Language: English
• Published: Chichester, West Sussex, U.K. : Wiley, 2011.
• Edition: 3rd ed.
• Subjects: VHDL (Computer hardware description language); Logic design > Data processing.; Computer-aided design.; VHDL (Bilgisayar donanımı tanımlama dili); Mantık tasarımı > Bilgi işlem.; Bilgisayar destekli tasarım.; COMPUTERS > Computer Engineering.; COMPUTERS > Logic Design.; TECHNOLOGY & ENGINEERING > Electronics > Circuits > Logic.; TECHNOLOGY & ENGINEERING > Electronics > Circuits > VLSI & ULSI.; Logic design / Data processing.; Electronic books.; Llibres electrònics.

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Table of Contents:

• Front Matter
• Introduction
• Register-Transfer Level Design
• Combinational Logic
• Basic Types
• Operators
• Synthesis Types
• Std_Logic_Arith
• Sequential VHDL
• Registers
• Hierarchy
• Subprograms
• Special Structures
• Test Benches
• Libraries
• Case Study
• Appendix A: Package Listings
• Appendix B: Syntax Reference
• References
• Index.