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03193nam a22004935i 4500 |
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978-1-4020-8092-0 |
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20151204144839.0 |
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100301s2004 xxu| s |||| 0|eng d |
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|a 9781402080920
|9 978-1-4020-8092-0
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|a 10.1007/b117251
|2 doi
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|d GrThAP
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|a TK7888.4
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|a TEC008010
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|a 621.3815
|2 23
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|a Chen, Pinhong.
|e author.
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|a Static Crosstalk-Noise Analysis
|h [electronic resource] :
|b For Deep Sub-Micron Digital Designs /
|c by Pinhong Chen, Desmond A. Kirkpatrick, Kurt Keutzer.
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|a Boston, MA :
|b Springer US,
|c 2004.
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|a XVIII, 113 p.
|b online resource.
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|a text
|b txt
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|a computer
|b c
|2 rdamedia
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|a online resource
|b cr
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|a text file
|b PDF
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|a Miller Factor Computation for Coupling Delay -- Convergence of Switching Window Computation -- Speeding-Up Switching Window Computation -- Refinement of Switching Windows -- Functional Crosstalk Analysis -- Conclusions.
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|a As the feature size decreases in deep sub-micron designs, coupling capacitance becomes the dominant factor in total capacitance. The resulting crosstalk noise may be responsible for signal integrity issues and significant timing variation. Traditionally, static timing analysis tools have ignored cross coupling effects between wires altogether. Newer tools simply approximate the coupling capacitance by a 2X Miller factor in order to compute the worst case delay. The latter approach not only reduces delay calculation accuracy, but can also be shown to underestimate the delay in certain scenarios. This book describes accurate but conservative methods for computing delay variation due to coupling. Furthermore, most of these methods are computationally efficient enough to be employed in a static timing analysis tool for complex integrated digital circuits. To achieve accuracy, a more accurate computation of the Miller factor is derived. To achieve both computational efficiency and accuracy, a variety of mechanisms for pruning the search space are detailed, including: -Spatial pruning - reducing aggressors to those in physical proximity, -Electrical pruning - reducing aggressors by electrical strength, -Temporal pruning - reducing aggressors using timing windows, -Functional pruning - reducing aggressors by Boolean functional analysis.
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|a Engineering.
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|a Computer-aided engineering.
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|a Electrical engineering.
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|a Electronic circuits.
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|a Engineering.
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|a Circuits and Systems.
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|a Electrical Engineering.
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|a Computer-Aided Engineering (CAD, CAE) and Design.
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1 |
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|a Kirkpatrick, Desmond A.
|e author.
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|a Keutzer, Kurt.
|e author.
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|a SpringerLink (Online service)
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|t Springer eBooks
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776 |
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8 |
|i Printed edition:
|z 9781402080913
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|u http://dx.doi.org/10.1007/b117251
|z Full Text via HEAL-Link
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912 |
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|a ZDB-2-ENG
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912 |
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|a ZDB-2-BAE
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950 |
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|a Engineering (Springer-11647)
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